1. Field of the Invention
The present invention relates to an asynchronous first-in-first-out cell, particularly to an asynchronous first-in-first-out cell, which not only can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies but also can apply to a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies.
2. Description of the Related Art
The principle of SOC (System on a Chip) design is to achieve high throughput and low latency. Although the performance of a chip can be promoted via increasing operation frequency, the power consumption of the entire chip system will rise obviously, and a great amount of heat is also generated thereby. Further, owing to the increasing communication time between chip modules, it is hard to distribute a single synchronous clock to the whole chip system. Therefore, a chip system not only needs a power management function and a DC-DC conversion function but also should be capable of lowering power consumption under different voltages. The GALS (Globally-Asynchronous Locally-Synchronous) system can handle asynchronous clocks, and in this interface, using asynchronous FIFO (first-in-first-out) cells as temporary storage devices can solve the abovementioned chip-system problems.
However, the conventional asynchronous FIFO design is implemented with the burst mode and a CAD tool, which causes not only further higher circuit complexity but also further more power consumption; therefore, it is hard to apply the conventional asynchronous FIFO design to a dual-supply-voltage system. The US Patents No. 20040128413 and No. 20020167336 disclose FIFO technologies, which can apply to the interface having different clock domains, such as synchronous-synchronous clock domains, synchronous-asynchronous clock domains and asynchronous-asynchronous clock domains; it utilizes a token mechanism and FIFO registers to determine the storage device where data is to be stored; in the synchronous clock domain, circular shift registers are used to form the token mechanism, and S-R (set-reset) flip-flops are used to form a state detector; in the asynchronous clock domain, a handshake controller, a CAD tool and the burst mode are used to obtain a put token, a get token and a data validity controller. However, from the overview of the US Patents No. 20040128413 and No. 20020167336, too many logic gates are used therein, which complicates the circuit structure and increases the power consumption.
Accordingly, the present invention proposes an asynchronous first-in-first-out cell, which not only can reduce circuit complexity and power consumption, but also can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies and a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies.